The invention relates to the design and manufacture of integrated circuits, and more particularly, to systems and methods for performing parallel processing of circuit components during the circuit design process.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, and wires, which are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
As the quantity of data in modern IC designs become larger and larger over time, the execution time required to process EDA tools upon these IC designs also becomes greater. For example, the more transistors and other structures on an IC design the greater amounts of time that is normally needed to perform placement and routing operations for that design. This problem is exacerbated for all EDA tools by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, as well resulting in more complex physical and lithographic effects during manufacture that need to be considered.
To achieve faster results, it is therefore desirable to perform EDA processing upon an IC layout using multi-processing approaches, e.g., concurrent or parallel processing. Parallel processing (also referred to as parallel computing) is a form of computing in which multiple operations are carried out simultaneously, or in “parallel.” Parallel computing operates on the principle that large problems can be divided into smaller ones, with each smaller problem addressed by individual processing units concurrently. Examples of systems that support parallel processing include multi-CPU/processor computers and distributed processing systems having multiple networked nodes. For example, for EDA tools, the process of designing a layout for an IC design may implemented in parallel by dividing the layout into separate partitions, and having separate processing units handle the placement and routing operations for each individual partition in the layout.
There are, however, significant obstacles for EDA vendors that wish to implement a parallel processing solution for IC layouts. Many of the obstacles relate to the need to take data dependencies and data conflicts into account to make sure that a first processing unit does not perform operations that negatively affect the data operated upon by a second processing unit.
One conventional EDA approach to address this problem is to utilize switchboxes to partition the layout. The switchbox is a partitioned unit of the layout that essentially appears as a black box to other portions the layout. A defined interface is used to connect the switchbox to the rest of the layout. Since the switchbox appears as a black box to the rest of the layout, the inner portions of the layout within the switchbox can therefore be processed independently of the other portions of the layout. As such, multiple switchboxes can be processed in parallel with minimal concerns of data conflicts. The problem with this approach is that there is a high cost to the process of stitching a switchbox to another portion of the layout. Under certain circumstances, those excessive costs to integrate the switchboxes could seriously diminish the potential benefits of using the switchboxes in the first place.
Therefore, there is a need for an improved approach to implement parallelization for EDA processing that avoids the high cost of existing approaches.